Modern integrated-circuit memory systems are often composed of independently selectable “ranks” of memory components, with each rank receiving a number of dedicated control signals from a control component. In a typical implementation, each memory rank receives a dedicated clock-enable signal to enable constituent memory components to be switched into and out of a low-power state without affecting other memory ranks, and a dedicated chip-select signal to enable the rank of memory components to receive and respond to memory access commands exclusively and thus without contention from components within other memory ranks. While the conventional control approach may be sufficient in legacy systems, memory rank proliferation due to advances in system architecture and component packaging have begun to strain system resources. In module-threaded systems, for example, individual ranks of memory components may optionally be operated as two or more smaller ranks, thus multiplying the requisite number of dedicated rank control signals, driving up control-component pin count and increasing system wiring complexity. The control signal count is similarly multiplied by packaging advances that permit memory components to be stacked or otherwise arranged in a manner that increases the number of memory ranks disposed within a given footprint (e.g., four, eight or more memory ranks per memory module instead of the traditional one or two), again, driving up pin count and increasing wiring complexity.